Welcome to this Verilog Fundamentals tutorial series. Verilog is the programming language that transforms hardware description into a programming language. It is literally called a Hardware Description Language (HDL). But wait a minute, “what exactly do you mean by hardware?” one might ask. Well, that is a very good question, because hardware could mean almost anything, right? Yes, well, generally speaking, if we break the word hardware into two (the linguistic exercise known as morphology), we get “hard” and “ware”. So we can loosely translate hardware as being “hard” “things” or “hard (solid) stuff”. Notwithstanding, within the Engineering domain, “hardware” has the more specific meaning of electronics, or at least the part of electronics that is not software. So in general, electronics engineering is split into the two sub-fields of hardware and software. We already know what software means, right? These are the programs we run on our computers. In order to work, software needs some hardware to run on, which does not particularly help our intuition of the subject of hardware versus software. Notwithstanding, hardware description languages like Verilog do not describe all electronics hardware. Only a subset of electronic hardware do HDLs deal with. This subset is called digital electronics. So Verilog is a HDL that describes digital electronics in a software programming language fashion, further blurring the lines of distinction between hardware and software. As confusing as this may sound, there are justifiable reasons to do this. The main advantage of describing hardware in software is the economy involved in producing pure hardware versus soft hardware. In other words, it is a lot cheaper, faster, more efficient, and ultimately more economical to produce hardware as software versus pure hardware.

Anyway, with the little introductory note on why Verilog out of the way, and if Verilog is something of interest, then let us dive into what is in store for us today in this article.

Prerequisites and Equipment

The focus for today is the tools and resources required to get started programming in Verilog. Before diving into the tools, one first needs to consider what prerequisite knowledge is required to program in Verilog. Usually, HDL is a subject taught at undergraduate level electronics, and it probably carries a higher learning curve than that of hobbyist electronics. That said, this article series attempts to make the material accessible to anyone with a high (secondary) school education.

The first piece of equipment one would require to program in Verilog is a computing device. If one is reading this online, there is probably already access to a computing device, whether that is a desktop, laptop, or mobile phone. In this series of articles, all of the above devices are supported. That said, the best experience will be found using either a desktop computer or a laptop computer. There is no guarantee that all the necessary tools will run on all of these devices, and the mobile phone will have the most limited support of the three.

Software CAD Tools

The remainder of this tutorial focuses on the software tools one will require to write and run Verilog programs. There are two paths to choose from. The first path is the one to follow for those who prefer to develop using an actual FPGA training board. Going down this route enables programming the training board with Verilog and allows experimentation with the results of a program using the FPGA board of choice. This will be of interest to those who love to experiment with hands-on exercises using physical devices. This is, however, the more expensive route, requiring the purchase of an FPGA development board. The other choice is using an HDL simulator. For this route, the EDA Playground online HDL simulator is the tool of choice. This series of tutorials has been designed to support both paths by providing parallel versions of the tutorials. If one prefers using an FPGA board, note that the software requirements are board specific. This series of tutorials uses Xilinx boards and Vivado software. However, there are other non-Xilinx boards using alternative software CAD tools. The most common would be Intel FPGA Altera devices and the accompanying Intel Quartus software. These other FPGA devices and their accompanying software follow similar Verilog development workflows, so it is entirely possible to follow along using those alternative platforms. However, only the details of Vivado and Xilinx will be covered in this series, and in particular this series of tutorials uses the Xilinx Basys3 development board. Newcomers may find these constraints somewhat challenging, and hence using the FPGA simulation path is the recommended starting point.

Conversely, if one decides to follow the FPGA simulation path, this is the path likely to have the widest coverage of readers of this blog series in terms of cost and platform compatibility. Also note that there are several simulation tools that can achieve the same goals as EDA Playground. For instance, Intel FPGA software ships with the ModelSim program, which performs FPGA simulation. However, here the focus will be on EDA Playground, as the online capability of using mobile browsers gives the mobile user some level of experimentation, even though it is not the ideal experience. Moreover, the online browser experience simplifies the setup process without the need to install any software at all. Having a web browser on the computing device is sufficient to get started programming Verilog.

Note: FPGA Board Track

From this point forward, this article covers the FPGA board track exclusively. All instructions assume that one has access to a Xilinx Basys3 development board and a personal computer running Windows (or Linux, where noted). If one does not yet have access to an FPGA development board, or prefers to begin without the additional hardware cost, the simulation track is covered in the parallel Episode 2 article in this series, which walks through the same Verilog concepts using the EDA Playground online simulator. One can return to this article and the FPGA board track at any point once a suitable board becomes available.

Downloading Vivado

The AMD Vivado design suite, previously published under the Xilinx brand before AMD acquired the company in 2022, is available in several editions. For this tutorial series, the Vivado ML Edition is the recommended choice. Without a paid licence, Vivado operates in WebPACK mode, which is the free tier of the toolchain. WebPACK mode supports the Artix-7 FPGA family to which the Basys3 board belongs, and it is fully capable of handling every project covered in this series without requiring the purchase of a software licence.

Before downloading, one will need a free AMD account. If one does not already have one, an account can be created at no cost directly from the download page. AMD requires account registration to track software licence agreements, even for tools used in WebPACK mode.

The download page is linked in the Resources section at the end of this article. Should that link be unavailable due to website maintenance or URL changes, the second resource link in that section provides a Google search for the term “download vivado”, which will locate the current AMD download page. If neither link works, searching for “download vivado” in any web browser will return the AMD download page as a top result.

Once on the download page, locate the “AMD Unified Installer for FPGAs and Adaptive SoCs”, which is the standard installer that handles Vivado and other AMD design tools. Select the most recent version available and choose the Windows installer from the listed options. The installer file is a self-extracting archive of approximately 1 to 2 gigabytes. Linux installers are also listed on the same page for those working on a Linux machine; the installation procedure for Linux is similar to the Windows process described below, with the principal difference being that the installer is launched from a terminal window rather than from a graphical file manager.

Before beginning the download, it is worth noting that while the installer file itself is compact, the installed Vivado toolchain requires a substantial amount of disk space. The installation steps in the next section guide one through selecting only the device support components needed for the Basys3 board, which reduces the installation size to approximately 20 to 30 gigabytes. Allocating at least 35 gigabytes of free disk space before proceeding is advisable.

Installing Vivado

Once the installer has been downloaded, locate it in the file manager, right-click the file, and select “Run as Administrator”. Running as administrator is recommended on Windows to ensure the installer has sufficient permissions to write to the necessary system directories and to install the USB cable drivers correctly.

The installer opens with a welcome screen confirming the version about to be installed. Click Next to proceed to the account sign-in screen. Enter the credentials of the AMD account created during the download step. If an account has not yet been created, a “Create Account” link is available on this screen. Sign in and click Next.

The product selection screen presents the AMD design tools available through the unified installer. Select “Vivado” from the list and click Next.

The edition selection screen lists the available Vivado editions. Select “Vivado ML Edition” and click Next. After installation, if no paid licence file is added, Vivado will operate in WebPACK mode automatically, which provides all the functionality needed for the Artix-7 device on the Basys3 board.

The component selection screen is the most important step for managing disk space. By default, Vivado selects support for all device families in its portfolio, which can consume upwards of 60 gigabytes. For this tutorial series, support is needed only for the 7 Series device family, which includes the Artix-7 on the Basys3 board. On this screen, deselect all device families except “7 Series”. Also ensure that “Vivado Design Suite” and “Install Cable Drivers” remain checked. With only the 7 Series devices selected, the installation size shown at the bottom of the screen should fall in the region of 20 to 30 gigabytes. Click Next.

Review the installation directory on the following screen. The default on Windows is C:\Xilinx, which is suitable for most users. If a different location is preferred, it can be specified here; however, avoid paths that contain spaces, as these can cause issues with certain Vivado project scripts. Click Next to reach the final summary screen, which confirms the total disk space required, and then click Install to begin the process.

The installation will take approximately 30 to 60 minutes depending on the speed of the machine and its storage device. A progress bar tracks each component as it is installed.

Towards the end of the installation, a separate dialogue box will appear requesting permission to install Xilinx USB cable drivers. These drivers are essential for communicating with the Basys3 board over the USB connection when programming the FPGA. Click Install to allow the driver installation to proceed. Without these drivers, Vivado will not be able to detect or communicate with a connected development board.

Once installation completes, Vivado can be launched from the Windows Start menu or from the desktop shortcut created by the installer.

Your First Basys3 Project: Switch to LED

With Vivado installed, one is ready to create a first FPGA project. This project connects a single slide switch on the Basys3 board to a single LED. Flipping the switch turns the LED on or off. It is the hardware equivalent of a “Hello, World” program: minimal in complexity, but it demonstrates the complete FPGA development workflow from writing Verilog source code to programming a physical device.

Before launching Vivado, connect the Basys3 board to the computer using a Micro-USB cable inserted into the USB port labelled “PROG” on the board. Power the board on using the small slide switch located beside the USB connector. The power LED on the board will illuminate to confirm it is receiving power.

Creating the Project

Launch Vivado. The main window opens with a Quick Start panel in the centre of the screen. Click “Create Project” to start the New Project wizard.

On the first wizard screen, enter a project name. “switch_led” is a suitable name for this project. Choose a folder on the computer where the project files will be saved, and ensure the “Create project subdirectory” checkbox is ticked so that all project files are kept together in one place. Click Next.

The project type screen appears next. Select “RTL Project” and leave “Do not specify sources at this time” unchecked, which allows source and constraint files to be added within the wizard itself. Click Next.

Adding the Verilog Source

The Add Sources screen allows one to add Verilog design files to the project. Click “Create File”, select “Verilog” as the file type, and enter “switch_led” as the file name. Click OK, then click Next.

After the wizard completes, Vivado may present a module definition dialogue asking one to specify port names and directions. This can be dismissed by clicking OK; the module content will be written manually in the next step.

In the Sources panel on the left side of the Vivado window, double-click the newly created switch_led.v file to open it in the text editor. Delete any automatically generated placeholder content and enter the following Verilog module:

// Verilog -- connect slide switch SW0 to LED LD0 on the Basys3 board
module switch_led(
    input  wire sw,    // connected to slide switch SW0
    output wire led    // connected to LED LD0
);
    assign led = sw;

endmodule

The assign statement is the simplest form of signal connection in Verilog. It creates a permanent, continuous connection between the input port sw and the output port led, meaning the LED will always reflect the state of the switch with no intervening logic. The module declares two ports and wires them together directly, which is precisely what is needed for this introductory project. Save the file with Ctrl+S. More complex forms of signal assignment, including the always block, will be introduced in a later episode when combinational and sequential logic circuits are covered.

Adding the Constraints File

A constraints file tells Vivado which physical pins on the FPGA correspond to the ports declared in the Verilog module. Without it, Vivado would have no way to determine which physical pin on the chip is wired to the switch and which is wired to the LED on the Basys3 printed circuit board.

In the Sources panel, right-click on “Constraints” and select “Add Sources”. On the Add Sources dialogue, choose “Add or create constraints” and click Next. Click “Create File”, select “XDC” as the file type, and enter “basys3_switch_led” as the file name. Click OK and then Finish.

Double-click the newly created .xdc file in the Sources panel to open it, and enter the following constraints:

## SW0 - Slide switch 0 is connected to FPGA physical pin V17
set_property PACKAGE_PIN V17     [get_ports {sw}]
set_property IOSTANDARD LVCMOS33 [get_ports {sw}]

## LD0 - LED 0 is connected to FPGA physical pin U16
set_property PACKAGE_PIN U16     [get_ports {led}]
set_property IOSTANDARD LVCMOS33 [get_ports {led}]

The PACKAGE_PIN constraint assigns a Verilog port name to a specific physical pin on the Artix-7 FPGA. Pin V17 is the FPGA pin wired to slide switch SW0 on the Basys3 board, and pin U16 is the pin connected to LED LD0. The IOSTANDARD LVCMOS33 constraint specifies the electrical signalling standard for those pins; the Basys3 board operates its switches and LEDs at 3.3 volts, making LVCMOS33 the correct standard for both. These pin assignments come directly from the Digilent Basys3 master constraints file, which lists every switch, LED, button, and connector on the board. Save the constraints file with Ctrl+S.

Running Synthesis

In the Flow Navigator panel on the left side of the Vivado window, click “Run Synthesis” under the Synthesis heading. Vivado analyses the Verilog module and translates it into a logical description using the FPGA’s available primitives. A progress dialogue tracks the stages of synthesis. For this simple design, synthesis completes in a matter of seconds.

When synthesis finishes, a dialogue box asks what to do next. Select “Open Synthesized Design” and click OK. It is worth taking a moment to inspect the results by selecting “Report Utilization” from the Reports menu. Because the switch_led design is a direct wire connection with no intervening logic, the utilization report will show zero LUTs (Look-Up Tables) consumed. This result offers an early glimpse into how Vivado optimises designs: it recognises that no logic cells are needed and routes the signal directly from the input pin to the output pin through the FPGA’s interconnect fabric.

Running Implementation

Close the synthesized design view and click “Run Implementation” in the Flow Navigator. Implementation takes the logical description produced by synthesis and maps it onto the specific physical resources of the Artix-7 device, determining exactly how each connection is placed and routed. For this design, implementation is brief. Click OK when the implementation complete dialogue appears.

Generating the Bitstream

Click “Generate Bitstream” in the Flow Navigator. The bitstream is the binary configuration file that will be loaded into the FPGA to define its internal logic connections. Vivado will re-run synthesis and implementation if required before generating the bitstream. A “Bitstream Generation Completed” dialogue will appear when the file is ready. Select “Open Hardware Manager” from the options presented and click OK.

Programming the Basys3 Board

The Hardware Manager is the interface between Vivado and the physical FPGA device. With the Basys3 board connected via USB and powered on, click “Open Target” in the green status banner at the top of the Hardware Manager, then click “Auto Connect”. Vivado searches for connected JTAG-capable devices and should detect the Artix-7 on the Basys3 board. The detected device will appear in the Hardware panel on the left side of the screen.

Click “Program Device” in the green banner, or right-click the detected device in the Hardware panel and select “Program Device”. A dialogue box will appear with the path to the bitstream file already populated; Vivado fills this in automatically from the active project. Click “Program” to transfer the bitstream to the board.

Programming takes only a few seconds. When it completes, the DONE LED on the Basys3 board will light up, confirming that the FPGA has been successfully configured with the new design. Flip slide switch SW0, the rightmost of the sixteen slide switches along the bottom edge of the board. LED LD0, the rightmost of the sixteen LEDs along the top edge, will turn on when the switch is pushed up and turn off when it is pushed down. The FPGA is now implementing a real hardware connection in silicon, driven entirely by the Verilog source and constraints files written in the steps above.

What Comes Next

Completing this project means one has successfully traversed the entire Vivado toolchain: writing a Verilog source file, creating a pin constraints file, running synthesis and implementation, generating a bitstream, and programming a physical FPGA. Every subsequent project in this series follows this same sequence, with progressively more capable Verilog designs replacing the simple passthrough.

Episode 2 of this series covers the simulation track in parallel, walking through the same Verilog concepts using EDA Playground. No FPGA board is required for Episode 2, and those who have followed the board track here may find it a useful complementary reference for understanding what the Vivado tools are doing during synthesis and implementation.

The following episode on the FPGA board track introduces the first Verilog language constructs beyond the wire and assign statement: logic gates, combinational circuits, and a first look at the always block. With Vivado installed and a working project workflow in hand, one is fully equipped to begin exploring the Verilog language in earnest.

Resources

The following links provide access to the Vivado download page. If the first link is no longer active due to website reorganisation or URL changes, the second link searches Google for the term “download vivado” and should locate the current AMD download page. If neither link works, searching for “download vivado” in any web browser will return the AMD download page as a top result.

• Vivado download link
• vivado downloads search

---

Glossary

always block A section of Verilog code that runs repeatedly whenever a specified signal changes. Unlike the assign statement, an always block can describe more complex behaviour including decision-making and sequential logic. It is introduced in a later episode of this series.

AMD The semiconductor company that acquired Xilinx in 2022. The Vivado design suite is now published under the AMD brand, though it is still widely referred to by its original Xilinx name.

Artix-7 The family of FPGA chips used on the Basys3 development board. The specific chip on the Basys3 is the XC7A35T. The “7 Series” option in Vivado’s device support list refers to this family.

assign statement A Verilog keyword that creates a permanent, continuous connection between two signals. Whenever the signal on the right-hand side changes, the signal on the left-hand side immediately follows. It is the hardware equivalent of a direct wire connection and contains no memory or decision logic.

Basys3 A widely used FPGA development board made by Digilent. It contains an Artix-7 FPGA chip and includes slide switches, LEDs, buttons, a VGA connector, and a USB programming port. It is the physical FPGA board used in the board track of this series.

bitstream The binary configuration file that programs an FPGA. When Vivado finishes synthesis and implementation, it generates a bitstream file that is transferred to the FPGA over USB. The bitstream defines all the internal logic connections inside the FPGA chip. Without a bitstream, the FPGA contains no logic and does nothing.

CAD tools (Computer-Aided Design tools) Software programs used to design, simulate, and verify electronic circuits. Vivado is a CAD tool for FPGA design; EDA Playground is a CAD tool for HDL simulation.

combinational logic Digital logic whose output depends only on its current inputs, with no memory of previous states. The assign led = sw connection in this article is combinational: the LED output always equals the switch input at every moment, with no clock required.

constraints file A file that tells Vivado which physical pins on the FPGA chip correspond to the named ports in the Verilog design. Without this file, Vivado cannot determine which pin is connected to which switch or LED on the circuit board. In this series the constraints file uses the .xdc extension.

development board A printed circuit board containing a programmable chip together with supporting components such as connectors, buttons, LEDs, and voltage regulators. Development boards make it easy to experiment with a chip without building custom hardware from scratch. The Basys3 is an FPGA development board.

digital electronics The branch of electronics that works with signals that have only two states: on (logic 1, high voltage) and off (logic 0, low voltage). All FPGAs, microcontrollers, and computers are built on digital electronics principles.

DONE LED A small LED on the Basys3 board that illuminates when the FPGA has been successfully programmed with a valid bitstream. It is the simplest confirmation that the programming step completed correctly.

Flow Navigator The panel on the left side of the Vivado window that provides buttons for each stage of the FPGA design process: synthesis, implementation, bitstream generation, and hardware programming. Clicking each button in sequence takes the design from Verilog source to a programmed FPGA.

FPGA (Field-Programmable Gate Array) An integrated circuit whose internal logic connections can be configured by the user after manufacture, by loading a bitstream file. An FPGA contains thousands of configurable logic blocks and interconnects that can be arranged to implement almost any digital circuit. “Field-programmable” means it can be reprogrammed in the field, as many times as needed, rather than being fixed at the factory.

Hardware Manager The section of Vivado that communicates with a connected FPGA development board over USB. It detects the board, identifies the FPGA chip on it, and is used to transfer the bitstream file to program the device.

HDL (Hardware Description Language) A programming language used to describe the structure and behaviour of digital electronic circuits. Unlike software languages that describe instructions for a processor, an HDL describes how logic gates and wires should be connected. Verilog is the HDL used throughout this series.

implementation The second major stage of the Vivado FPGA design flow, following synthesis. Implementation takes the logical description produced by synthesis and maps it onto the specific physical resources of the FPGA chip, deciding exactly where each piece of logic is placed and how connections are routed between elements.

input port A named signal on a Verilog module that receives data from outside the module. In the switch_led module, sw is an input port representing the state of the slide switch.

IOSTANDARD A Vivado constraint that specifies the electrical voltage level a physical FPGA pin should use. LVCMOS33 means the pin operates at 3.3 volt logic levels, which matches the switches and LEDs on the Basys3 board.

JTAG A standard hardware interface used to program and debug electronic devices. Vivado uses a JTAG connection over USB to transfer bitstream files to the Basys3 board. The Basys3 has an onboard USB-to-JTAG chip so that a standard micro-USB cable is all that is needed to program the FPGA from a PC.

LVCMOS33 The electrical standard used for the switches and LEDs on the Basys3 board. “LV” means low voltage, “CMOS” refers to the transistor technology, and “33” means 3.3 volts. A logic high on these pins is 3.3 V; a logic low is 0 V.

LUT (Look-Up Table) The basic configurable logic element inside an FPGA. A LUT is a small block of memory that can implement any logical function of a fixed number of input signals. When Vivado synthesises a Verilog design, it maps the described logic into LUTs on the FPGA. The utilisation report after synthesis shows how many LUTs the design consumed. Because switch_led is a direct wire connection with no logic, it consumes zero LUTs.

module The fundamental building block of a Verilog design. A module is a self-contained unit of hardware description with a defined set of named input and output ports. The keyword module begins the definition and endmodule ends it.

output port A named signal on a Verilog module that sends data out from the module. In the switch_led module, led is an output port representing the state of the LED.

PACKAGE_PIN A Vivado constraint that connects a port name in the Verilog design to a specific physical pin number on the FPGA chip. For example, set_property PACKAGE_PIN V17 [get_ports {sw}] connects the Verilog port sw to physical pin V17, which is the chip pin wired to slide switch SW0 on the Basys3 board.

port A named input or output connection on a Verilog module. Ports are how a module communicates with the outside world. See also: input port, output port.

RTL (Register-Transfer Level) A style of Verilog that describes how data moves between registers and what logical operations are performed on it. RTL Verilog is synthesisable, meaning Vivado can convert it into actual hardware on an FPGA. All Verilog in this series is written as RTL.

RTL Project A project type in Vivado indicating that the design is specified in synthesisable RTL Verilog. This is the correct project type to select when following the tutorials in this series.

signal Any named value that can change over time in a digital design. A signal may represent the state of a switch, the output of a logic gate, or a clock. In Verilog, signals are represented as wire or reg types depending on how they are driven.

simulation Running a software model of a hardware design to observe how it behaves without requiring physical hardware. The parallel Episode 2 article in this series uses the EDA Playground simulator to run the same switch_led design without an FPGA board.

synthesis The first major stage of the Vivado FPGA design flow. Synthesis analyses the Verilog source code and translates it into a logical description built from the FPGA’s available primitive components, such as LUTs and flip-flops. The result is a netlist describing the required logic, before any decisions are made about where on the chip each element will be placed.

Verilog A Hardware Description Language used to describe digital electronic circuits. A Verilog file describes what a piece of digital hardware should do: which signals it has, how they are connected, and what logic operates on them. The same Verilog source can be used to simulate a design on a computer or to program it onto an FPGA.

Vivado The FPGA design software suite published by AMD (formerly Xilinx). It provides tools for writing Verilog, running synthesis, performing implementation, generating bitstream files, and programming FPGA development boards over USB. Vivado WebPACK is the free edition used in this series.

WebPACK mode The free tier of Vivado, available without a paid licence. WebPACK mode supports a defined subset of AMD FPGA devices including the entire 7 Series family, to which the Artix-7 on the Basys3 belongs. All projects in this series are fully supported without purchasing a software licence.

wire A Verilog data type representing a connection that is continuously driven by another signal or by an assign statement. A wire cannot hold a value on its own; it always reflects whatever is driving it. The output port led in the switch_led module is a wire because it is continuously driven by the assign statement.

XDC (Xilinx Design Constraints) The file format used by Vivado to specify physical constraints on a design. An XDC file contains set_property commands that connect port names to physical FPGA pins (PACKAGE_PIN) and specify their electrical standards (IOSTANDARD). Every Vivado project targeting a physical FPGA board requires an XDC file.

Xilinx The semiconductor company that created the Vivado toolchain and the Artix-7 FPGA family. Xilinx was acquired by AMD in 2022. The name still appears throughout the toolchain and in community documentation.